The present invention relates generally to computer memory, and more specifically, to tagging in a memory control unit (MCU).
Contemporary high performance computing main memory systems are generally composed of one or more memory devices, which are connected to one or more memory controllers and/or processors via one or more memory interface elements such as buffers, hubs, bus-to-bus converters, etc. The memory devices are generally located on a memory subsystem such as a memory card or memory module and are often connected via a pluggable interconnection system (e.g., one or more connectors) to a system board (e.g., a PC motherboard).
Overall computer system performance is affected by each of the key elements of the computer structure, including the performance/structure of the processor(s), any memory cache(s), the input/output (I/O) subsystem(s), the efficiency of the memory control function(s), the performance of the main memory devices(s) and any associated memory interface elements, and the type and structure of the memory interconnect interface(s).
Extensive research and development efforts are invested by the industry, on an ongoing basis, to create improved and/or innovative solutions to maximizing overall system performance and density by improving the memory system/subsystem design and/or structure. High-availability systems present further challenges as related to overall system reliability due to customer expectations that new computer systems will markedly surpass existing systems in regard to mean-time-between-failure (MTBF), in addition to offering additional functions, increased performance, increased storage, lower operating costs, etc. Other frequent customer requirements further exacerbate the memory system design challenges, and include such items as ease of upgrade and reduced system environmental impact (such as space, power and cooling). In addition, customers are requiring the ability to access an increasing number of higher density memory devices (e.g., DDR3 and DDR4 SDRAMs) at faster and faster access speeds.
In view of varying cost, capacity, and scalability requirements, a wide number of memory system options may need to be considered. Often a choice needs to be made between using an asynchronous boundary between a processor and memory buffer chips or designing a fully synchronous system. An asynchronous design allows the flexibility of running the processor at a fixed frequency, while memory buffer chips can be programmed to varying frequencies to match the desired memory components. For example, if cost is most important, a slower more widely available dual in-line memory module (DIMM) can be used. In contrast, if performance is paramount, then a leading edge technology DIMM can be used. This type of memory system architecture may work well in systems where each memory channel runs independently. However, this approach typically falls short in high-availability systems.
Redundant array of independent memory (RAIM) systems have been developed to improve performance and/or to increase the availability of storage systems. RAIM distributes data across several independent memory modules, where each memory module contains one or more memory devices. There are many different RAIM schemes that have been developed, each having different characteristics, and different pros and cons associated with them. Performance, availability, and utilization/efficiency (e.g., the percentage of the memory devices that actually hold customer data) are perhaps the most important. The tradeoffs associated with various schemes have to be carefully considered because improvements in one attribute can often result in reductions in another. Examples of RAIM systems may be found, for instance, in U.S. Patent Publication Number 2011/0320918 titled “RAIM System Using Decoding of Virtual ECC”, filed on Jun. 24, 2010, the contents of which are hereby incorporated by reference in its entirety, and in U.S. Patent Publication Number 2011/0320914 titled “Error Correction and Detection in a Redundant Memory System”, filed on Jun. 24, 2010, the contents of which are hereby incorporated by reference in its entirety.
High availability systems, such as RAIM systems, can include a number of clock domains in various subsystems. Efficient integration of subsystems including different clock domains presents a number of challenges to establish synchronization timing, detection of synchronization issues, and recovery of synchronization.
In computer memory, reliable delivery of data from system memory with minimal latency may result in complexity in MCU design. A MCU may return blocks of data from system memory to a cache subsystem. The computer memory may include dynamic random access memory (DRAM) chips, and data is delivered from the DRAM to the MCU on multiple high-speed memory channels. A MCU may recover from intermittent or permanent single channel failures by distributing data within a block across multiple channels, along with redundancy information. This allows the MCU to recover from failures on a per-data-block basis. A per-channel error detection mechanism, such as cyclic redundancy check (CRC), may also be provided.
If a non-permanent error occurs during the return of data in response to a read command on a single channel (e.g., CRC decoding detects an error), the original read command may be re-issued by the MCU to provide more robust error recovery. In order to re-issue a memory read command, the MCU retains the original command until the requested data is received with no errors across all channels. Write commands to memory may also be retained until it is known that the data was successfully received by the computer memory across all channels. The MCU must maintain a fixed data relationship across all channels in order to control retrying of read or write commands in the event of an error detected on a single channel.